The disclosed invention generally relates to frequency synthesizers and is more particularly directed to a phase-locked frequency synthesizer having a sample-and-hold phase detector with variable sampling efficiency for providing an adaptive loop bandwidth.
Frequency synthesizers are commonly employed to generate a frequency or frequencies based on a reference frequency. A commonly utilized technique is known as phase-locked or indirect frequency synthesis. Phase-locked frequency synthesizers are extensively described in the published art including for example "The Digiphase Synthesizer," by Garry C. Gillette, a paper presented in 1969 at the twenty-third Annual Frequency Control Symposium; "Low-Noise Frequency Synthesizers Using Fractional N Phase-Locked Loops," Ulrich Rhode, RF Design, January/February 1981, pp. 20-34; "A Synthesized Signal Source with Function Generator Capabilities," Dan D. Danielson and Stanley E. Froseth, Hewlett-Packard Journal, January, 1979, pp. 18-26; "Frequency Synthesis: Techniques and Applications," J. Gorski-Popiel, IEEE Press, 1975; and "Frequency Synthesis by Phase Lock," William F. Egan, John Wiley & Sons, 1981. Other examples of phase-locked frequency synthesizers include U.S. Pat. No. 4,290,028, issued to Jesse S. LeGrand on Sept. 15, 1981; U.S. Pat. No. 4,330,758, issued to Scott N. Swisher et al on May 18, 1982; and U.S. Pat. No. 4,437,407, issued to Daniel J. Healey, III et al on Feb. 28, 1984.
Phase-locked frequency synthesizers typically include a voltage controlled oscillator (VCO) which provides the output frequency. The VCO output frequency is coupled via a variable ratio frequency divider circuit to a phase detector. The reference frequency provides another input to the phase detector which provides an error signal for controlling the VCO. When the loop is locked, the two inputs to the phase detector have a constant phase relation and therefore the same frequency. The output of the VCO would then have a frequency equal to the reference frequency multiplied by the inverse of the divider circuit ratio.
Many types of phase detectors are utilized in phase-locked frequency synthesizers, including balanced mixers, high-speed samplers, exclusive-OR circuits, flip-flop circuits, and sample-and-hold circuits.
While phase-locked frequency synthesizers generally provide satisfactory performance, implementations are typically based on trade-offs between phase-lock acquisition performance and steady-state operation (phase-lock) performance. Simply stated, optimum phase-lock acquisition and optimum steady-state operation to some degree require different circuit characteristics. Particularly, an increased loop bandwidth provides for faster phase-lock acquisition, while a decreased loop bandwidth provides for steady-state operation with better spurious signal (sampling spurs) and phase noise performance. As a rseult, one condition may be optimized to the detriment of the other, depending on specific applications.
The problem of acquisition performance versus steady-state performance is significant in phase-locked frequency synthesizers which utilize sample-and-hold phase detectors. During acquisition, sample-and-hold phase detectors need to be fast, and the loop bandwidth must be increased to reduce phase-lock acquisition time. Phase-lock acquisition time may be particularly reduced by increased sampling efficiency. However, increased loop bandwidth and/or high high sampling efficiency results in increased phase noise and sampling spurs during steady-state operation.
An approach to optimizing both the acquisition performance and steady state performance in phase-locked frequency synthesizers involves utilizing a variable loop bandwidth. Thus, a particular loop bandwidth is utilized for acquisition while another loop bandwidth is utilized for steady-state operation. An example of a variable loop bandwidth system is disclosed in the previously cited patent to Swisher.
However, varying the loop bandwidth generally perturbs the steady-state condition. For example, the bandwidth change may occur over several sample periods, or the bandwidth change may also change the open loop again function. As a result, the phase-lock acquisition performance is degraded since acquisition time is effectively increased. Moreover, known variable loop bandwidth phase-locked frequency synthesizers tend to be complex and inefficient.